| 摘要 |
PURPOSE:To secure a system which takes out output data in a form of parallel signal and aligns the phase of the parallel signal to be outputted, that is, TSSI (Time Slot Sequence Integrity), by delaying an inputted serial digital signal by a prescribed number of bits by a variable length shift register provided at the front step of a serial-parallel conversion circuit. CONSTITUTION:A frame synchronization pattern is detected from either plural frame synchronization pattern detection circuits (300-1-300-n) provided in parallel, and the position of the pattern at parallel arrangement is detected by a synchronizing position detecting means 600. Corresponding to the above, a control signal which delays an input signal so as to set a frame synchronizing signal at the beginning of the parallel arrangement is added on a signal delay means 500, and the signal delay means 500 delays the input signal by the number of bits decided by the control signal. In such a way, the frame synchronizing signal is set at the forefront of the parallel output of the serial-parallel conversion circuit 200, and no mixing of the data of a preceding and a succeeding frames can be prevented from occurring, and also, the TSSI can be secured. |
