| 摘要 |
PURPOSE:To shorten a pull-in time until phase synchronization is taken, by constituting a circuit in such a way that the phase synchronization is taken with a pull-in range larger than a prescribed range until the establishment of the phase synchronization, and the phase synchronization is taken with the prescribed pull-in range after the establishment of the phase synchronization. CONSTITUTION:Phase alignment is performed similarly as ever by using 4-frequency division signals (8) and (9) out of signals in which a signal (1) generated from a master oscillator 1 by control signals (12) and (13) is frequency-divided until the phase synchronization is established. After the establishment of the phase synchronization, the phase alignment is performed similarly as ever by using 2-frequency division signals (2) and (3) out of the signals in which the signal (1) generated from the master oscillator 1 is frequency-divided. In such a way, it is possible to obtain a phase synchronization circuit where the pull-in time to the phase synchronization is shortened, and also, jitter is reduced.
|
