| 摘要 |
PURPOSE:To form the address of more than the bit width of a computing element at one clock cycle in an execution by calculating a next data transfer address by the computing element from a current address output to a next address output. CONSTITUTION:A control signal LDP is inputted from a control circuit 4 to a register 5 in order to shift the contents of an address register 2 to the pipe line register 5. Then, a memory is made access by the contents of the register 5 and a next output address is simultaneously calculated by a computing element 1. Thereafter, a control signal is set to HIGH and the high order 16 bits of the registers 2, 3 is simultaneously inputted to the computing element to execute the operation of the address. After this operation, the contents of the high order 16 bits of the register 2 are updated to the arithmetic output of the computing element 1. At this time, the contents of the register 2 go to the next address and the next address can be outputted from the register 5 at one clock cycle.
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