发明名称 DIGITAL ARITHMETIC CIRCUIT
摘要 PURPOSE:To realize a limit processing without increasing the number of devices, by providing an adder and a specific control circuit. CONSTITUTION:An input value 10b expressed in a natural binary of N bits and an input value 10a expressed in the complement of 2 of N bits are added by the adder 4, And in a case where the logic value of a carry output 49 is equal to that of the most significant bit 19, an added value 40 is set as an output value 60 by an output switching circuit 6, and in the case where the logic value of the carry output 49 is different from that of the most significant bit 19 and also the logic value of the most significant bit 19 is '0', the maximum value expressed in the natural binary is set as the output value 60, and in the case where the logic value of the carry output 49 is different from that of the most significant bit 19 and also the logic value of the most significant bit 19 is '1', the minimum value expressed in the natural binary is set as the output value 60. In such a way, it is possible to obtain a digital arithmetic circuit having an output characteristic to perform a desired limit processing.
申请公布号 JPS63262909(A) 申请公布日期 1988.10.31
申请号 JP19870096605 申请日期 1987.04.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OMOTANI YOSHIRO;SATO TOSHICHIKA
分类号 G06F7/38;G06F7/508;H03G11/00 主分类号 G06F7/38
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