| 摘要 |
PURPOSE:To prevent unnecessary data from being loaded to a cache memory, by transferring a data block in which an address of the data concerned is the head, to the cache memory, in case its data does not exist in the cache memory. CONSTITUTION:In case the data concerned does not exist in a cache memory 4 due to a cache miss, a data block containing the data concerned is brought to a block transfer to the memory 4 from a main memory 2. In that case, to a block address counter 12, the upper bits A31-A2 of a processor address signal 7 are loaded. When the block transfer is started, the counter 12 is brought to an increment whenever 4 bytes are loaded, and it is outputted as an address signal to the main memory 2. After this block transfer has been completed, a processor 1 reads the data concerned from the cache memory 4, and a read cycle is completed.
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