| 摘要 |
PURPOSE:To facilitate the design of the timing of a clock signal of a shift register by constituting a shift register circuit by utilizing output terminals led out through delay circuits provided to plural FF circuits. CONSTITUTION:A FF circuit 101 has a normal FF circuit 201 and a delay circuit 241 the output 254 of the circuit 201 is sent out as a SQ output 253 through the circuit 241. Then even when the timing of the clock (CLK) of the circuit 101 faster than the CLK timing of the circuit 102 owing to the delay difference between logic circuits 121 and 122, the value of the SQ before the CLK of the circuit 101 is inputted can be fetched with the output SQ passed through the delay circuit 241 of the circuit 101, so the shift register operates normally. The shift registers of the FF circuits 102-105 operate similarly. The shifting operation is used only in a scan path test, so the delay circuit 241 exerts any influence on normal operation. |
