发明名称 FAST SYNCHRONIZATION CIRCUIT
摘要 PURPOSE:To secure TSSI(Time Slot Sequence integrity), by providing a cross- connect switch which outputs a parallel signal of (n) bits whose phase is aligned from the input of a parallel signal of (2n-1) bits outputted from a serial-parallel conversion circuit. CONSTITUTION:A frame synchronizing pattern is detected from either plural frame synchronizing pattern detection circuits(300-1-300-n) arranged in parallel is detected, and it is added on the input on one side of a signal switching means 500 as a control signal. Meanwhile, the parallel signal of (2n-1) bits outputted from the serial-parallel conversion circuit 200 is added on the input on the other side of the signal switching means 500. And a switch 5 is switched by the control signal from a frame synchronizing pattern detecting means, and the parallel signal of (n) bits in which a frame synchronizing signal is set at the front and whose phase is aligned is outputted. In such a way, the frame synchronizing signal is set at the front of the parallel output of the cross- connected switch 5, and no mixture of the data of a preceding and a succeeding frames is prevented from occurring, and the TSSI can be secured.
申请公布号 JPS63262939(A) 申请公布日期 1988.10.31
申请号 JP19870097733 申请日期 1987.04.20
申请人 FUJITSU LTD 发明人 MIURA NORIHISA;TAKEO HIROSHI;TAKEDA SATOSHI;NAKADE HIROSHI;YAMAZAKI HIROSHI
分类号 H04J3/06;H04J3/00;H04L7/08;H04L13/10;H04L25/40 主分类号 H04J3/06
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