| 摘要 |
PURPOSE:To decrease factors preventing the high speed operation of a transistor such as parasitic capacitance, and base resistance, by forming all of the following in a manner of self-alignment; an aperture for base lead-out part, an outer base region, an aperture for emitter lead-out part, an intrinsic base region, and an emitter region. CONSTITUTION:By an etching applying an oxide film 10 on P polysilicon 6 to a mask, the P polysilicon 6 and a nitride film 5 are selectively eliminated, and an aperture 11 for base lead-out part is formed. After the thermal oxide film 10 is eliminated, polysilicon is again grown, and a sidewall 12 is formed by an anisotropic etching. Thus a base pull-out part is formed, and then an insulating oxide film 15 is formed. In this case, an outer base layer 13 is formed, by impurity diffusion from the P polysilicon through the aperture for base lead-out part. Finally, the nitride film of an emitter region is eliminated, and an aperture for emitter lead-out part is formed. After that, a P-type base layer 17 and an N-type emitter region 18 are formed, by impurity diffusion from the grown N polysilicon 16 through the aperture for emitter lead-out part. Thereby, parasitic capacitance and base resistance are reduced, and do not prevent the high speed operation of a transistor.
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