| 摘要 |
PURPOSE:To fine and speed-increase a bipolar transistor and a CMOS FET simultaneously by adding a specific process to the manufacturing process of a normal Bi-CMOS LSI. CONSTITUTION:Low-concentration N-type layers 22 are formed into a collector electrode region in a bipolar transistor and source-drain regions in an N channel MOS FET, low-concentration P-type layers 23 are shaped into a base region in the bipolar transistor and source-drain regions in a P channel MOS FET, and N<+> or P<+> diffusion layers 11 and 13 are formed through ion implantation. A second polysilicon layer 18 is shaped into a region corresponding to an emitter in the bipolar transistor prior to ion implantation at that time, and the second polysilicon layer is also formed onto the side wall of a polysilicon gate electrode 9 previously. Accordingly, the fine bipolar transistor operating at high speed and the N channel and P channel MOS FETs can be formed simultaneously.
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