TRISTATE ENABLE GATE WITH POWER SUPPLY THRESHOLD ACTIVATION CIRCUIT

摘要

An improved tristate enable circuit is described for activating a tristate enable gate to maintain the high impedance third state of a common bus tristate output device during "power down" and "power up" transitions of the common power supply Vcc. The enable gate circuit element tends to turn off at a voltage level Vcc2 generally greater than the voltage level Vcc3 at which the tristate output device circuit elements turn off. As a result the high impedance state may be lost during "power down". A threshold activation circuit is coupled to the enable gate for activating the enable gate when the threshold activation circuit senses a higher common power supply voltage level Vcc1. The threshold activation circuit operatively activates the enable gate over a voltage range from Vcc1 to a lesser common power supply voltage level Vcc4. Component values are selected for relating the voltage levels so that Vcc1>Vcc2 and Vcc3>Vcc4. As a result the turn off of circuit elements is sequenced by the threshold activation circuit.