发明名称 CLOCK FREQUENCY DIVISION CIRCUIT
摘要 PURPOSE:To cope with the request of a clock signal economically by outputting a clock signal having a frequency relating to a ratio of values between two sets of integral numbers from a basic clock signal depending on a count output of a count means. CONSTITUTION:In receiving a switching signal Sa from a changeover means 300 in a clock frequency division circuit, a carry signal co is outputted from a count means 100 at each Na period of a basic clock signal mck and in receiving a signal sb, the signal co is outputted at each Nb period of the signal mck. A means 300 outputs a signal sa when the count n2 of a 2nd count means 200 belongs to a count group n2a and outputs a signal sb when the count n2 belongs to the count group n2b. Thus, the ratio of number of times of the output of the signal co at the periods Na, Nb of the signal mck from the means 100 is decided by arranging number of the count n2 of the means 200 belonging to the count groups n2a, n2b. Then the clock signal of the frequency relating to a ratio between the two sets of integral numbers Na, Nb is outputted from the signal mck.
申请公布号 JPS63260222(A) 申请公布日期 1988.10.27
申请号 JP19870093916 申请日期 1987.04.16
申请人 FUJITSU LTD 发明人 MATSUNAGA KOJI
分类号 H03K23/64;H03K23/66 主分类号 H03K23/64
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