| 摘要 |
PURPOSE:To miniaturize the hardware and to make it suitable for the formation of LSI by executing all communications with a host computer only through a bus. CONSTITUTION:The titled processor is constituted so that all the communications between processor elements 7 and the host computer 1 can be executed through an external bus and an internal bus EB, IB. For the processing of a certain algorithm, only such parameters as necessary for the processing are transmitted from the host computer 1 to each of the respective processor elements 7 through the internal and the external buses EB, IB, then the data to be processed are sequentially transmitted to all the processor elements 7 by broadcasting. Lastly, the results of the processings are transmitted from the processor elements to the host computer through the buses. In such a way, the processing is sped up speedified. Also, since all data transmission can be executed through the internal and the external busses IB, EB, the formation of LSI is facilitated, and thus the miniaturization can be attained. |
