| 摘要 |
PURPOSE:To read out plural addresses at one time by arranging plural transfer gates in parallel with each other and connecting different read address terminals to those transfer gates respectively. CONSTITUTION:A memory cell contains a read address terminal RA, a read data terminal RD, write data terminal the inverse of WD and WD, a write address terminal WA, a write enable terminal WE, inverters G11-G13, and the transfer gates Q11-Q15. In a data read state only the terminal RA is set at 'H' and the holding data on the terminal RD is outputted with inversion of bit. In a data write state the terminal WA is set at 'H' and one of both terminals the inverse of WD and WD is set at 'H' or 'L' together with the terminal WE set at 'H' respectively. Thus the data on the terminals the inverse of WD and WD are read. Then (n) pieces of such memory cells are gathered and a data writing circuit, a write address decoder and a read address decoder are provided in common to a group of said memory cells. Thus a memory circuit is formed.
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