发明名称 INFORMATION PROCESSING SYSTEM
摘要 PURPOSE:To simultaneously read-in the same microprogram in plural information processors, and to shorten initialization time by providing read-in completion detection circuits on a loader at every word. CONSTITUTION:The loader 2 is provided with not only a load control circuit 5 but read-in completion detection circuits 9 at every word. The load control circuit 5 instructs simultaneously all the information processors to read-in the same microprogram. Then, the read-in completion detection circuit 9 at every word detects that the read-in of all the information processors at every word which read-in said microprogram is completed, and informs it to the load control circuit 5. Thus, plural information processors can simultaneously read-in the same microprogram, and consequently, the initialization time can be shortened.
申请公布号 JPS63259725(A) 申请公布日期 1988.10.26
申请号 JP19870094439 申请日期 1987.04.17
申请人 NEC CORP 发明人 YAHIRO KENJI
分类号 G06F9/24;G06F9/22;G06F9/445;G06F13/00 主分类号 G06F9/24
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