SEMICONDUCTOR MEMORY DEVICE CONTAINING MOS BIPOLAR COMPOSITE MULTIPLEXER CIRCUIT

摘要

PURPOSE:To increase the memory reading speed by using a bipolar transistor to drive plural common data lines. CONSTITUTION:In a bit line selecting circuit 5, a column selecting signal is set at 'L' for a selected column and a MOSFET having a large gm conducts with a bit line pair pulled up by VCC. The information on a memory cell of the line designated by a word line is produced on a bit line. In a selected block of a block selecting circuit 7, the bipolar transistors TRQ1 and Q2 start the emitter follower actions by the conduction of the TRT12 and T13. Thus the bit line information on the selected column is produced on a 1st common data line. While the information on the 1st common data line is produced on a selected data line of a selected block via the TRT14 and T15. A data line driving circuit 8 consists of the bipolar TRQ3 and Q4 and the information on the selected data line of the selected block is produced on a 2nd common data line.