发明名称 INTERFACE SYSTEM FOR COPROCESSOR
摘要 PURPOSE:To speed up operation speed by providing an FIFO (First In First Out) in the interface part of a coprocessor, and making the acceptance of statement in the coprocessor into a pipe line. CONSTITUTION:An FPU (Floating point Processing Unit) 101 is provided with a FIFO to fetch the DATA of a data bus 105 related to a command or an operand, and the FPU101 operates on receiving signals AT2-AT0 to indicate the kind of an access from a CPU100 and execute a coprocessor protocol by returning the signals CPST2-CPST0 to the CPU100. Thus, since a command pipe line is possible, the overhead of the interface in the floating point operation can be reduced, and the operation speed can be speeded up.
申请公布号 JPS63259727(A) 申请公布日期 1988.10.26
申请号 JP19870093098 申请日期 1987.04.17
申请人 HITACHI LTD;HITACHI ENG CO LTD 发明人 MORINAGA SHIGEKI;NAKAGAWA NORIO;WATABE MITSURU;OBA MAMORU;KIDA HIROYUKI;KAJIWARA HISASHI;ASAI TAKESHI;TATEZAKI JIYUNICHI
分类号 G06F7/00;G06F9/38;G06F15/16;G06F15/167 主分类号 G06F7/00
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