| 摘要 |
PURPOSE:To connect the output terminal group of plural memories with an external data bus so as to easily realize wired AND, by providing an open drain outputting and external data bus precharging functions in addition to a tri-state outputting function. CONSTITUTION:An output circuit composed of a 1st control means (b) which outputs 1st and 2nd input data N1 and N2 to 1st and 2nd outputs N4 and N5, respectively, when a 1st control signal phiE is high in level and a low level when the signal phiE is low in level, a 2nd control means (a) which outputs the positive- phase amplification signal of memory cell data D when a 2nd control signal F is high in level and a low level when the signal F is low in level, and a 3rd control means B which raises the gate potential of a 1st MOS transistor 1 only when a 3rd control signal phiP is low in level, is provided. Therefore, the output terminal group of plural memories can be connected with an external data bus and wired AND data can be obtained.
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