发明名称 REFRESHING CONTROL CIRCUIT
摘要 <p>PURPOSE:To realize power saving to a system using a DRAM with a simple circuit configuration, by using clocks which are different from ordinary clocks at the time of the power saving mode and a CPU whose clock is set at a low speed and performing refreshment on the DRAM. CONSTITUTION:Oscillation means 107 and 108 which generate clocks in the power saving mode, a selecting means which switches clocks between ordinary clocks and power saving mode clocks, and a refreshing means 104 which refreshes a DRAM 101 by means of a CPU 103 whose clock is set at a low speed, are added to a component. In other words, the oscillation means 107 and 108 generate clocks of the power saving mode and the selecting means 109 makes switching operation between the ordinary clocks and power saving mode clocks. The refreshing means 104 performs refreshment on the DRAM 101 by using a CPU 103 whose clock is set at a low speed. Therefore, the power consumption of this system using the DRAM can be saved with a simple circuit configuration.</p>
申请公布号 JPS63257995(A) 申请公布日期 1988.10.25
申请号 JP19870090988 申请日期 1987.04.15
申请人 TOSHIBA CORP 发明人 HIBI KENJI
分类号 G11C11/401;G06F1/00;G06F1/08;G11C11/34;G11C11/406 主分类号 G11C11/401
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