| 摘要 |
PURPOSE:To avoid the competition of data by generating an output control signal to keep the output to the high impedance (Hi-Z) condition for a constant time in the internal part and controlling the output after a reading mode is ascertained. CONSTITUTION:A counter circuit 3 to receive a detecting high level signal outputted from a reading mode ascertaining detecting circuit 1 counts the necessary number of the cycles of the pulse from an oscillating circuit 2 and a high level signal is outputted for a constant time. In a RAM write cycle in which a write enable low level is delayed and ascertained after a chip selecting low level is ascertained, an output buffer 4 and an output control 5 are kept in a non-active condition by the signal outputted from the counter circuit 3 and an I/O terminal comes to be the Hi-Z output condition in the constant time without fail. Thus, the correspondence of the bus of write data without an output enable terminal function, to occur at the time of the write cycle of an I/O common RAM and from a CPU and output data from the RAM can be prevented.
|
