| 摘要 |
PURPOSE:To apply a folded bit line system even at the time of a memory cell structure suitable to a high integration by forming respective bit lines to form a pair with a different wiring layer and crossing them at a suitable place. CONSTITUTION:Bit lines BL0,... connected through a contact, word lines WL0,... and a transfer gate to a memory cell are formed, for example, by a third layer poly Si layer, arranged in an upper direction, form a pair with the bit lines formed by a wiring layer (for example, Al wiring layer) different from this and are inputted to a sense amplifier SA0,.... Further, the bit lines to form a pair are crossed at a middle point C in the length direction and interchanged. Thus, a bit line capacity to form the pair is balanced, a memory cell structure suitable to a high integration is never changed and the sense system of a folded bit line can be easily realized.
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