发明名称 SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To prevent the timing when an obtained output signal pulse from being retarded by 1/2(H) during the period when the equivalent pulse exists even if the equivalent pulse is missing because of the changeover of heads by obtaining a horizontal synchronizing signal with an equivalent pulse eliminated therefrom from a composite synchronizing signal and a pseudo pulse. CONSTITUTION:A video signal inputted from a terminal 1 is inputted to a composite synchronizing signal separating circuit 2, where the composite synchronizing signal is separated. Moreover, the head changeover signal inputted from a terminal 3 is inputted to a pseudo pulse generating circuit 4, from which a pseudo pulse is generated. The composite synchronizing signal and the pseudo pulse are added by an adder 5, the added signal is inputted to a gate circuit 6, where an undesired equivalent pulse is eliminated. The signal with the undesired equivalent pulse eliminated therefrom is inputted to an inhibition circuit 7. The inhibition circuit 7 eliminates an undesired pulse caused by the addition of the composite synchronizing signal and the pseudo pulse based on the information of the composite synchronizing signal obtained at the composite synchronizing signal separating circuit 2. The output signal of the inhibition circuit 7 from which the undesired pulse is eliminated is outputted from a terminal 8 as the horizontal synchronizing signal.
申请公布号 JPS63256073(A) 申请公布日期 1988.10.24
申请号 JP19870090249 申请日期 1987.04.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HOSOKAWA NOBUO;HONJO MASAHIRO;KOBAYASHI MASAAKI
分类号 H04N5/93;G11B20/02 主分类号 H04N5/93
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