发明名称 SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To prevent timing when an obtained output signal pulse from being retarded by 1/2(H) during the period when an equivalent pulse exists even if the equivalent pulse is missing because of the changeover of heads by obtaining a horizontal synchronizing signal with an equivalent pulse eliminated from a composite synchronizing signal and a pseudo pulse. CONSTITUTION:A video signal inputted from a terminal 1 is inputted to a composite synchronizing signal separating circuit 2, where a composite synchronizing signal is separated. Moreover, a head changeover signal inputted from a terminal 3 is inputted to a pseudo pulse generating circuit 4, from which a pseudo pulse is generated. The pseudo pulse obtained by the composite synchronizing signal separated from the composite synchronizing signal separating circuit 2 and the pseudo pulse obtained by the pseudo pulse generating circuit 4 are given respectively to an equivalent pulse elimination circuit 5, where an undesired equivalent pulse is eliminated. The signal with the undesired equivalent pulse eliminated therefrom is outputted from the terminal 6 as a horizontal synchronizing signal.
申请公布号 JPS63256075(A) 申请公布日期 1988.10.24
申请号 JP19870090251 申请日期 1987.04.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HOSOKAWA NOBUO;HONJO MASAHIRO;KOBAYASHI MASAAKI
分类号 H04N5/93;G11B20/02 主分类号 H04N5/93
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