发明名称 LEVEL DETECTION CIRCUIT
摘要 PURPOSE:To certainly detect a level by a simple constitution, by providing the first comparator for comparing input signal voltage with lower limit voltage and the second comparator for comparing the input signal voltage with the signal voltage of a time constant circuit. CONSTITUTION:A standard potential source 23 sets the voltage signal V2 high level of a signal C when the input signal Vb of a terminal 21 becomes higher than the lower limit value V2. At this time, an FET 24 is turned ON and the voltage signal V1 of an upper limit value is supplied to the input terminal of the second comparator 30 on the reversal side thereof and the comparator 30 outputs the high level y2 of a signal B to an alarm apparatus when the signal Vb exceeds the upper limit value V1 to make it possible to generate an alarm signal. When the signal Vb becomes lower than the lower limit value V2, the comparator 22 outputs the low level of the signal C and the FET 24 is turned OFF and, since a time constant circuit formed by a condenser 26 and resistors 27, 28 supplies gradually lowering signal potential Vc to the comparator 30, the signal Vb becomes higher than the potential Vc and the comparator 30 outputs the high level x2.z2 of the signal B to the alarm apparatus to generate an alarm signal.
申请公布号 JPS63255601(A) 申请公布日期 1988.10.21
申请号 JP19870090554 申请日期 1987.04.13
申请人 SONY MAGNESCALE INC 发明人 SANO JUNICHI;HIRUTA AKITAKA;YAMADA SHIGERU
分类号 G01B7/00;G01D5/245;G01R19/165 主分类号 G01B7/00
代理机构 代理人
主权项
地址