发明名称 CONTROL SYSTEM FOR MEMORY ERROR
摘要 PURPOSE:To ensure a smooth shift to error recovering processing without stopping the working of a processor by measuring the output time for error occurrence state signals for a prescribed time after the output of the error occurrence state signal and delaying information on the error occurrence state signal to the processor based on said measured output time. CONSTITUTION:A memory reading time measuring circuit 2 measures the output time of the error occurrence state signals for a prescribed time after the output of the error occurrence state signal. Then a response signal generating circuit 1 delays the information on the error occurrence state signal to a processor 15 based on said measured time of the circuit 2. Thus it is possible to prevent malfunction and a hang-up state of the processor 15 and therefore to avoid a system breakdown due to disturbance noises produced temporarily and at random when a memory data error occurs. As a result, the system working time is extremely increased and a processor system can be smoothly processed.
申请公布号 JPS63254547(A) 申请公布日期 1988.10.21
申请号 JP19870089550 申请日期 1987.04.10
申请人 MITSUBISHI ELECTRIC CORP 发明人 KOJIMA TORU
分类号 G06F12/16;G06F13/00 主分类号 G06F12/16
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