发明名称 SEMICONDUCTOR INTEGRATED LOGIC CIRCUIT
摘要 PURPOSE:To shorten a test time by adding an output level setting circuit to which a selector has been added, to the pre-stage of an output buffer of a semiconductor integrated circuit, so that an output level can be set easily at the time of measuring DC characteristic. CONSTITUTION:To input terminals A3 of selector circuits D1-Dm of 3 bits for outputting a signal of A when control inputs S1, S2 are '00', that of C at the time of '01', that of B at the time of '10', and '0' at the time of '11', outputs of an internal logic circuit 1 are connected, respectively, and an input terminal A1 and A2 are fixed to a high level and a low level, respectively, and to its post-stage, output buffers B1-Bm, respectively. Also, at the time of regular use, control signals SE1, SE2 are fixed to '01' so that an internal logical output signal is outputted as it is, and at the time of measuring a DC characteristic, the output can be fixed to a high level or a low level by inputting '00' or '10' to the control signals SE1, SE2.
申请公布号 JPS63253273(A) 申请公布日期 1988.10.20
申请号 JP19870088019 申请日期 1987.04.10
申请人 NEC CORP 发明人 NISHIYAMA KEIICHI
分类号 G01R31/28;H01L21/66;H01L21/822;H01L27/04 主分类号 G01R31/28
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