发明名称 MOS INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To remove the waste of an area in a semiconductor substrate, and to scale down the size of a semiconductor chip by forming specified stepped structure between a metallic conductor for a bonding pad and a metallic conductor for a wiring. CONSTITUTION:An oxide film 3 on a semiconductor substrate 1 is removed through a contact process extending over a scheduled region corresponding to the position of arrangement of a metallic conductor 4 as a bonding pad, and stepped structure by the oxide film 3 is shaped. The metallic conductor 4 as the bonding pad is disposed onto a buried layer 2 under the state in which it is housed into the stepped structure of the oxide film 3. A metallic conductor 5 as a wiring is arranged onto the oxide film 3. Consequently, even when a spread is generated in the metallic conductor 4 as the bonding pad by pressure at the time when a metallic small-gage wire is bonded, the metallic conductor 4 is not short-circuited to the metallic conductor 5. Accordingly, a space X between the metallic conductor 4 as the bonding pad and the metallic conductor 5 as the wiring can be shortened maximally.
申请公布号 JPS63253646(A) 申请公布日期 1988.10.20
申请号 JP19870088050 申请日期 1987.04.10
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 KITAO ICHIRO
分类号 H01L23/52;H01L21/3205;H01L21/60 主分类号 H01L23/52
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