| 摘要 |
PURPOSE:To facilitate the circuit integration by providing an integration circuit using an output of a differentiation circuit as the input so as to reduce the capacitance of a capacitor of the integration circuit. CONSTITUTION:An adder 1 adds an input signal In and an offset cancel signal Oc of an output of an integration circuit 9 to cancel the offset component of the input signal In and outputs the result. A switch circuit 12 of the integration circuit 9 is conducted by a differentiation pulse generated when the down position of an updown counter 4 overflows and a prescribed positive charge is injected to the capacitor C1 by a constant current source 10 to increase the potential by one step. Moreover, a switch circuit 13 is conducted when the up-position of the counter 4 overflows and a prescribed negative charge is injected to the capacitor C1 by the constant current source 11 to decrease the potential by one step. Thus, zero correction is applied by using a potential integrated by the capacitor C1 having a time constant depending on the frequency of the input clock CL.
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