| 摘要 |
PURPOSE:To prevent wrong locking operations and perform quick locking operations, by counting clocks locked by a PLL and setting a follow-up control ling circuit to its initialized state, and then, cancelling the locking of the PLL. CONSTITUTION:The oscillating frequency of a VFO 1 and cutoff frequency of an LPF 4 are controlled by means of the follow-up controlling signal of a follow-up controlling circuit 3 which is outputted in accordance with data read out from a disk, etc., and the clock of sampling signals is locked by a closed loop PLL composed of a phase comparator 2 and the LPF 4 and VFO 1. When the clock is counted by a counting circuit 5 and the counted value of the circuit 5 becomes larger than a prescribed value because the clock is locked to frequency signals of two times larger or no synchronizing signal is produced at the time of counting a prescribed number under an unstable condition where the state of the PLL does not make transition until the number of clocks reach a fixed value, the follow-up controlling circuit 3 is set to its initialized state by means of reset signals from the circuit 5 and the VFO 1 can restore to its self-running state. Therefore, wrong locking operations can be prevented and quick locking operations can be performed.
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