ARITHMETIC PROCESSOR

摘要

PURPOSE:To realize a high-speed arithmetic operation with no addition of a hardware by providing a carry transmission gate and an extension enable signal. CONSTITUTION:When an instruction decoding unit DEC 40 decodes a 64-bit arithmetic instruction, a microprogram address of an address calculation controller ICNT 510 is produced so that an address calculating 32-bit computing element IALU 300 can be controlled via an instruction execution controller ECNT 610. Then an FF 516 is set and a carry transmission gate 310 is set under an enable state. The high-order 32 bits are set at an address calculation internal register IREG 350 with the low-order 32 bits set at an instruction execution internal register EREG 450 respectively. Then both high-order and low-order 32-bit arithmetic operations are carried out at one time by the IALU 300 and an instruction executing 32-bit computing element EALU 400 respectively. Thus both the IALU 300 and the EALU 400 work as a single 64-bit computing element and high-order and low-order 32 bits are set at the IREG 350 and EREG 450 respectively. In such a way, it is possible to perform the high-speed arithmetic operation that exceeds the operable data width of an instruction executing unit with no addition of the hardware.