| 摘要 |
PURPOSE:To improve the overall processing capacity of a system by performing the simultaneous reading and writing jobs over two words by an amount equal to the 1-word length when data are transferred over the word boundary between a main memory and a main memory access device and arranging the data on a bus to end the reading and writing jobs while the 1-word data is transferred. CONSTITUTION:The 1-word length data is read out of an address w0 shown by an intra-word selection address bus 30 in an address w1 shown by a word selection address bus 29 by an access request given from a main memory access device 15. Under such conditions, both the data on a submemory covering the w0-th place through the n-th place of a submemory address w1 and the data on the submemory covering the 0-th place through the (w0-1)-th place of a submemory address (w1+1) are read out at one time. Then an intra-word array changing circuit, 19 rearranges those data into the 1-word length data as mw0,..., mn, m0,..., mw0-1. Thus the transfer of data is through in the bus cycle of a single time. Then the bus application rate is halved in terms of a single word for the transfer of data between a main memory 14 and the device 15. As a result, the overall system performance is improved.
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