发明名称 EMITTER-COUPLED LOGIC CIRCUIT
摘要 PURPOSE:To realize power consumption with a low level and to accelerate a processing, by connecting the collectors of switching transistors to the emitters of emitter follower transistors, respectively, and connecting the base of the emitter follower transistor on one side to the collector of the emitter follower transistor on the other side, and the base of the transistor on the other side to the collector of the transistor on one side. CONSTITUTION:Assuming that a signal of level L is inputted to an input terminal 1N, the transistor Q1 is turned OFF, and the transistor Q2 is turned ON. By turning OFF the Q1, a Q3 is also turned OFF, and when the Q3 is turned OFF, the collector potential of the Q3 goes to almost the ground potential. Thereby, from an output terminal Out2 and an output terminal, the inverse of Out2, voltages lower than an output terminal Out1 and an output terminal, the inverse of Out1 by a voltage between the bases and the emitters of a Q4 and the Q3 are outputted, and the output terminals, the inverse of Out2 and the Out2 become low impedance outputs. In such a way, a Miller effect can be suppressed, and a capacitance between the base and the collector of the Q1 and the Q2 by appearances when being observed from the input terminal 1N is reduced. In such a way, a fast processing can be realized.
申请公布号 JPS63250914(A) 申请公布日期 1988.10.18
申请号 JP19870084992 申请日期 1987.04.07
申请人 YAMAHA CORP 发明人 HIROMOTO MASASHI
分类号 H03K19/086 主分类号 H03K19/086
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