发明名称 PULSE COUNTING CIRCUIT
摘要 PURPOSE:To decrease power consumption by using the intermediate condition of the start and completion of counting in the counting action of respective systems. CONSTITUTION:A latch and subtracting circuit 7-1 obtains how many clock pulses a counter 5-2 counts. A counter 5-1 makes the subtracting value of the latch and subtracting circuit 7 into an initial value, the output of a coincidence detecting circuit 6-2 is used as trigger and the pulse counting of the clock signal supplied from a clock signal input terminal 2 is started. The coincidence detecting circuit 6-1, when the counting value of the counter 5-1 comes to be a constant value set beforehand, outputs the pulse signal, resets an RS flip flop 4-1 and the counter 5-1 and starts the counting action of the counter 5-2. Thus, when either of counters 5-1 and 5-2 is operated, other counter is stopped, and even when it is stopped, the counting information of a counter 5-1 or 5-2 during the action is used and the clock pulse can be correctly counted.
申请公布号 JPS63250218(A) 申请公布日期 1988.10.18
申请号 JP19870085173 申请日期 1987.04.06
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SAWAHASHI MAMORU
分类号 H03K23/66;H03K5/05 主分类号 H03K23/66
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