发明名称 |
Partial write control apparatus |
摘要 |
In a partial write control apparatus for a memory having a high speed operation mode such as a nibble mode or a page mode, when a partial write request for a plurality of words including those which require partial write is received, a memory control signal generator causes the memory to read successively all the words requiring partial write in a single high speed operation mode read cycle. A merging circuit merges those portions of the read-out words which need no alteration with write data and forms a group of updated complete words. Then, the memory control signal generator causes the memory to write successively these words in a single high speed operation mode write cycle.
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申请公布号 |
US4779232(A) |
申请公布日期 |
1988.10.18 |
申请号 |
US19870052546 |
申请日期 |
1987.05.20 |
申请人 |
HITACHI, LTD. |
发明人 |
FUKUNAKA, HIDETADA;IKEDA, KOICHI |
分类号 |
G06F12/04;G11C7/00;G11C7/10;(IPC1-7):G11C7/00;G11C11/40 |
主分类号 |
G06F12/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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