发明名称 JUDGEMENT OF FLAW IN INSPECTION OF WIRING PATTERN OF PRINTED CIRCUIT BOARD
摘要 PURPOSE:To shorten an inspection time, by applying simultaneous scanning to the same places of three sets of wiring patterns equal to each other to obtain three sets of contour data and comparing the first arbitrary data not only with the second data but also with the third data. CONSTITUTION:Three printed circuit boards 2-1, 2-2, 2-3 having the same wiring pattern are arranged to a base plate 1'. Flaw detectors 3-1, 3-2, 3-3 are provided corresponding to the boards 2 and area illuminations 4-1, 4-2, 4-3 of halogen beam are performed from the flaw detectors to apply sampling scanning to the same areas of the wiring patterns of the boards 2-1, 2-2, 2-3. The detection signals of the detectors 3 are subjected to data processing to obtain contour data A1, A2, A3 wherein the characteristics of contours are shown at sampling base points. Comparison is performed at every base points with respect to two sets of combinations wherein two among three sets of the contour data are arbitrarily selected. By this method, a flaw detection time can be shortened.
申请公布号 JPS63249042(A) 申请公布日期 1988.10.17
申请号 JP19870083436 申请日期 1987.04.03
申请人 HITACHI ELECTRONICS ENG CO LTD;HITACHI CHEM CO LTD 发明人 YOSHIZAWA TAKAO;HORIUCHI MASAYUKI;NITTA NORIYUKI;MURAMATSU MOTOHIKO
分类号 G01N21/88;G01N21/93;G01N21/956;H01L21/66 主分类号 G01N21/88
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