发明名称 PRIORITY INTERRUPTION CIRCUIT
摘要 PURPOSE:To reduce the burden of software of a microprocessor, by determining precedence with hardware in the external of the microprocessor to be interrupted. CONSTITUTION:An encoder circuit 8 discriminates the interruption of the highest priority of output lines P1''-P8'' and outputs a 3-bit code signal 9 corresponding to this interruption and an intrruption request signal INT to a buffer circuit 10 and a microprocessor 1 respectively. When detecting the interruption request signal INT, the microprocessor 1 and its peripheral parts jump to each interruption program and set a bit in a reset port 4 through a data bus 3. Then, an interruption signal of a latch circuit 6 is reset to make it possible to accept the interruption again. The microprocessor 1 sets a mask port 5 in accordance with an executing program, thereby supplying only a non-masked interruption signal to the encoder circuit 8 through a gate circuit 7.
申请公布号 JPS5998257(A) 申请公布日期 1984.06.06
申请号 JP19820207861 申请日期 1982.11.26
申请人 MATSUSHITA DENKI SANGYO KK 发明人 IMADA HIROSHI
分类号 G06F9/48 主分类号 G06F9/48
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