| 摘要 |
PURPOSE:To reduce the circuit scale and also to increase the multiplying speed by shifting the interim result of the product sum with use of the algorithm of a booth. CONSTITUTION:The three low-order bits of a multiplicand D stored in a register 4 and a multiplier C stored in a register 5 where 0 of a single bit is added at the LSB side are supplied to an arithmetic circuit 6. Then a partial product R1 between the multiplicand D and the multiplier C is obtained based on the algorithm of a booth and held by a register 8 via an adder 7. The multiplier C is shifted to the lower rank side by 2 bits in the register 5 together with three low-order bits outputted to the circuit 6 for execution of a prescribed arithmetic operation. While the value held by the register 8 is multiplied by 1/4 through a shift circuit 9 and added with the output of the circuit 6 via the adder 7 to be held by the register 8 again. Hereafter the same operation is carried out for acquisition of the results of multiplication. |
