| 摘要 |
PURPOSE:To reduce the size of a memory cell and realize high-speed refreshing, by using a write/read address input line, read data output line, and refresh data input line as common communication lines. CONSTITUTION:When a write (W) input terminal 5 is set to 'H' and W transistors (Tr) 9 and 11 are set to conducted states, data inputted from W data input terminals 1 and 2 are accumulated in capacitors 25 and 27 through the Trs 9 and 11. When a W input terminal 6 is set to 'H' thereafter. W Trs 10 and 12 are turned on and the data inputted from the terminals 1 and 2 are accumulated in capacitors 26 and 28, and thus, writing is executed. When read (R) data output terminals 3 and 4 are precharged and R address input terminals 1 and 2 are set to 'H', and then, R Trs 17 and 18 or 19 and 20 are turned on at the time of readout, inverted signals of write data are outputted to the R data output terminals 3 and 4. Refreshed data are extracted from the R data output terminals 3 and 4 and inverted into the terminals 3 and 4 after inversion.
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