发明名称 CHANNEL SELECTION CONTROL CIRCUIT
摘要 PURPOSE:To attain simple channel selection control circuit with time delay by outputting band switching data and channel data serially from a microcomputer and separating them in a shift register so as to convert them into the band switching voltage and the tuning voltage. CONSTITUTION:A channel selection data SLCT is outputted serially from the microcomputer 5 in synchronism with a clock CLK at the channel selection and AFT operation by the user. The 1st 2-bit is the band switching data BAND and the remaining 14-bit is a channel data CHNL. Moreover, a strobe signal STRB representing the signal output is outputted. The data SLCT, the clock CLK and the signal STRB are fed to a 16-bit serial input/parallel output shift register 6. Two-stage outputs (1), (2) of the register 6 are fed to a tuner circuit 1 via the decoder 3 as a band switching voltage VB and the remaining 14-bit output is fed to the circuit 1 via a D/A converter 7 as the tuning voltage VC.
申请公布号 JPS63246086(A) 申请公布日期 1988.10.13
申请号 JP19870080314 申请日期 1987.03.31
申请人 SONY CORP 发明人 SATO MASAHIKO;OKADA YOSHIKI
分类号 H04N5/44 主分类号 H04N5/44
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