Method for clock synchronisation

摘要

The invention relates to a method for clock synchronisation in a receiver for digital data transmission comprising a clock phase detector into which the in-phase and quadrature component, no longer containing the signal terms of the doubled frequency due to low-pass filtering, of the demodulated received signal which is produced from the product of the received signal by the output signal of the carrier oscillator as input signal, are input and are logically combined to form two control signals in such a manner that these two control signals uTR and uTI can be interpreted as real part and imaginary part of a complex control variable uT = uTR + juTI, the two control signals uTR and uTI being subjected to an averaging and then the values/uTR,/TI thus averaged are evaluated by means of an evaluating circuit to form a drive variable by means of which the clock phase correction circuit is driven, and is characterised by the fact that a logic circuit is provided in which the two averaged control signals /uTR and /uTI are logically combined, that the complex/uTR-/uTI- plane is divided into two regions (1, 2) that region 1 contains the positive uTR- semiaxis and region 2 contains the negative uTR- semiaxis, that the logic operation is carried out in such a manner that it is determined whether the vector point represented by uTR, uTI is located in region 1 and that, if this is so, the logic circuit (lacuna) a signal ... Original abstract incomplete. <IMAGE>