| 摘要 |
PURPOSE:To attain high output without prolonging a chip size laterally by using conventional gallium arsenide field effect transistor GaAs FETs in series. CONSTITUTION:For example, sources of two GaAs FETs 1 and drains of FET 2 are connected and the drain of the FET 1 is used as a drain voltage supply terminal and a PF output terminal and a source of the FET 2 is connected to ground. The gate of each FET is connected to gate bias voltages VG1, VG2 by using resistors R1-R3. The voltages VG1, VG2 are selected to be -1--3V being a gate bias of a conventional GaAs FET while the relation of V1-Vc=Vb-Vd exists where V1, Vb are voltages at nodes (a), (b) and Vc, Vd are voltages of nodes (c), (d). Thus, the voltage fed to the drain of the FET 1 is divided by the FETs 1, 2 and the gate-drain voltage is at a normal operating level, then the dielectric strength is doubled in comparison with a conventional circuit without overload.
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