| 摘要 |
PURPOSE:To remarkably reduce the hardware by adopting divided plural reception signal registers and plural impulse reply registers corresponding to the reception signal registers so as to reduce the quantity of arithmetic calculation per sample. CONSTITUTION:Reception signal and impulse response registers are divided into respective three registers, that is, 1st-3rd reception signal registers 251-253 and 1st-3rd impulse response registers 261-263. Then an impulse response register selection circuit 33 controls so as to update the contents of the 1st-3rd impulse response registers 261-263. Thus, the quantity of arithmetic operation in one sample is reduced to nearly 2/3 in comparison with a conventional canceller, as (6N+2) number of times of multiplication into (4N+2) number of times and (6N+2) number of times of addition/subtraction into (4N+2) number of times, assuming 3N is the number of taps.
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