| 摘要 |
PURPOSE:To reduce the number of FFs for select signal holding by holding a select signal in accordance with a current selected clock signal outputted from an OR circuit. CONSTITUTION:When a select signal SEL is '1', Q and the inverse of Q outputs of a D-FF 11 are '1' and '0' respectively and Q outputs of D-FFs 46 and 48 are '1' and '0' respectively. Consequently, a clock signal CLK1 is outputted as a clock signal CLK3 because AND circuits 40 and 41 are turned on and off respectively. When the signal SEL goes to '0', Q and the inverse of Q outputs of the FF 11 go to '0' and '1' respectively. The Q output goes to '0' because the Q output of the FF 11 goes to '0'. Consequently, the signal CLK3 is stopped. The Q output of the FF48 goes to '1' after the inverse of Q output of the FF11 goes to '1'. Next, the circuit 41 is changed to the turning-on state and a clock signal CLK2 is outputted as the signal CLK3. By this constitution, the number of FFs where the signal SEL is held is reduced to one. |
