SEMICONDUCTOR LOGIC INTEGRATED CIRCUIT

摘要

PURPOSE:To surely prevent the fetch of an erroneous data by selecting a pulse width of an enable signal opening a latch of a data latch circuit obtained from a timing circuit. CONSTITUTION:A timing circuit 4 consists of an asynchronous hexadecimal counter using four edge trigger type flip-flops 411-414, a NOR gate 42 and two edge trigger flip-flops 43, 44 at an output section. Signals Load 1 and Load 2 which are obtained from the timing circuit 4, and being timing pulses to control the data latch switching are both '1' pulses. Since the timing signals Load 1 and Load 2 are '1' pulses and have a shorter pulse width than the clock period T, no malfunction takes place in data latch.