发明名称 PARALLEL A/D CONVERTER
摘要 PURPOSE:To obtain the converted waveform over the entire period of a clock pulse by providing a charge storage capacitor and a switch circuit supplying an emitter current source synchronously with a clock to an encoder line and shifting the level of the output of a logic circuit synchronously with the clock. CONSTITUTION:The encoder lines 111, 112 provided with charge storage capacitors 121, 122 and switch circuits 81-86, 141-144 supplying emitter current sources 131, 132 synchronously with a clock and the output of logic circuits 51-53 is level-shifted synchronously with a clock. Thus, the voltage generated at a half period of the clock pulse 160 is stored during the remaining half period as the charge in the capacitor of the encoder lines 111, 112. Thus, the converted waveform nearly over the entire period of the clock pulse is obtained.
申请公布号 JPS63245019(A) 申请公布日期 1988.10.12
申请号 JP19870077732 申请日期 1987.03.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUZAWA AKIRA;YAMADA HARUYASU
分类号 H03M1/36 主分类号 H03M1/36
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