发明名称 PROCESSOR FAULT DETECTING SYSTEM
摘要 PURPOSE:To reduce the load of a master processor by transmitting a life/death checking signal from the master processor by a multiple address communication format, and when a time limit has lapsed, discriminating an unanswered slave processor as a fault. CONSTITUTION:A life/death checking signal is transmitted from a fault detecting means 111 in the master processor 110 to slave processors 120, 130, 140 by the multiple address communication format through a loop bus 100. The life/ death checking signal is received by life/death answering means 121, 131, 141 in respective slave processors. When the slave processor is in a normal state, a prescribed answer signal is transmitted from its corresponding life/death answering means to the master processor 110 through the loop bus 100. The answer signal is received by the means 111 in the processor 110. The slave processor generating no answer signal when a prescribed time limit has lapsed from the transmission of the life/death checking signal is discriminated as a fault.
申请公布号 JPS63245734(A) 申请公布日期 1988.10.12
申请号 JP19870081528 申请日期 1987.04.01
申请人 NEC CORP 发明人 KOKUBU AKEMI
分类号 G06F11/16;G06F11/20;G06F15/16;G06F15/177;H04M3/22 主分类号 G06F11/16
代理机构 代理人
主权项
地址