| 摘要 |
<p>Certain stored program digital computer systems employ a single central memory to which requests are made for individual instruction words stored within it. Certain types of these memories employ address queues in which requests may be temporarily stored when requests come in more rapidly than the central memory can service them. A write valid memory records each central memory request and provides a status signal which can be used to prevent placing of a further request for the word at an address in the queue.</p> |
