| 摘要 |
PURPOSE:To extremely reduce a counting error even when the counting of a pulse is performed in arbitrary timing, by providing a means for converting the cycle of the pulse train converted by a pulse train converter in inverse proportion to the power data calculated by a multiplier. CONSTITUTION:Analogue input voltage (v) and an analogue current (i) are respectively converted by A/D converters 1, 2 to be inputted to a multiplier 3 and multiplied at every generation timing of a multiplication cycle signal and power data is outputted in parallel. The power data and the multiplication cycle signal are inputted to a pulse train converter 5 and a variable frequency divider 7. The converter 5 outputs the signal obtained by dividing the frequency of the oscillation signal of an oscillator 6 by the variable frequency divider 7 at every multiplication cycle as a pulse train composed of a number of the pulses corresponding to the power data. The frequency divider 7 controls a frequency dividing ratio so as to be inversely proportional to the magnitude of the value of the power data at each time when said data is inputted to output the frequency signal corresponding to the power data to be converter 5. Therefore, the cycle of the pulse train outputted from the converter 5 is averaged at every cycle and the pulse train is brought to almost continuous pulses and an error is almost eliminated even in the counting of arbitrary timing. |
