| 摘要 |
PURPOSE:To decrease hardware quantity and to realize the simple control by controlling parallel cache memories by applying a write-back system using three states to control the access request given to its own area occupying the greater part of a memory access and controlling the access request given to other areas by sending them to a shared bus. CONSTITUTION:A shared memory 3 is divided and allocated to each cache memory 2 corresponding to each processor 1 and circuits 22a and 22b holding start and end addresses of the area of each memory 2 are provided. Furthermore each processor 1 contains the commands for change of the contents of both address holding circuit 22a and 22b. Then the access request given to the data in its own area of the divided memory 3 is controlled by a write-back system. While the access requests given to the data in other areas of the memory 3 are sent to a shared bus 4 for control. Thus the parallel cache memories can be controlled in a simple way.
|
