| 摘要 |
A vector processing apparatus has a number of pipeline arithmetic units operating concurrently to execute a set of vector instructions dealing with vector elements. Stack registers are provided for each arithmetic unit to hold the vector instruction address, leading vector element position and vector register internal address, so that one of the exceptions that can be detected successively by several arithmetic units during the process of the vector instructions is selected on a priority basis through the comparison of information in the stack of the currently detected exception with information of exception detected previously.
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