| 摘要 |
PURPOSE:To correct a circuit design drawing with no change of modes after verification of the circuit design drawing by performing both the production processing and the verification processing of the circuit design drawing in parallel with each other with functions of a storage means and a control means. CONSTITUTION:When an enable signal A is outputted from a CPU 14, an address signal is outputted to delay specification data memory 13 from a drawing production/verification mode command memory 11. Thus the memory 13 is accessed by said address signals. In other words, delay calculation can be carried out in parallel with each other in the drawing production and verification modes with output of the signal A. When the CPU 14 outputs an enable signal B, the memory 13 is accessed by an address signal received from the CPU 14. In such a way, the drawing can be produced and verified at one with use of the memory 11.
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